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Freescale Semiconductor Data Sheet: Technical Data
Document Number: DSP56724EC Rev. 1, 12/2008
DSP56724/DSP56725
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors
The Symphony DSP56724/DSP56725 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using dual DSP56300 24-bit cores. The DSP56724 is intended for consumer and professional audio applications that require high performance for audio processing. In addition, the DSP56724 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, DVD Receivers, Home Theater in a Box (HTIB), and professional audio equipment including portable recording equipment, musical instruments, guitar amplifiers and pedals. The DSP56724 offers customers flexibility in their designs by providing a more cost-effective alternative to the DSP56720 while maintaining pin compatibility. The DSP56725 is intended for automotive and audio applications that require high performance for audio processing. Potential applications include A/V receivers, DVD Receivers, Home Theater in a Box (HTIB), and automotive amplifiers and entertainment systems. The DSP56725 offers customers flexibility in their designs by providing a more cost-effective alternative to the DSP56721 while maintaining pin compatibility. The DSP56724/DSP56725 devices provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56724/DSP56725 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56724/ DSP56725 device can replace dual-DSP designs, saving costs while
DSP56724 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitch DSP56725 80-Pin LQFP 14 mm x 14 mm 0.65 mm pitch See Table 19.
meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/37x families are included, as are a variety of new modules available in the DSP5672x family. Modules from the DSP56720 are included, such as an Asynchronous Sample Rate Converter (ASRC), an Inter-Core Communication (ICC) module, an External Memory Controller (EMC) to support SDRAM (DSP56724 only), and a Sony/Philips Digital Interface (S/PDIF) transceiver. The DSP56724/DSP56725 devices offer up to 250 million instructions per second (MIPs) per core using an internal 250 MHz clock. The DSP56724/ DSP56725 products are high density CMOS devices with 3.3 V inputs and outputs. The DSP56724 block diagram is shown in Figure 1; the DSP56725 block diagram is shown in Figure 2.
NOTE
This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed.
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Chip-Level Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 7 1.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 8 1.1.6 Internal Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.7 External Clock Operation. . . . . . . . . . . . . . . . . . . . . 9 1.1.8 Reset, Stop, Mode Select, and Interrupt Timing . . 10 1.2 Module-Level Specifications . . . . . . . . . . . . . . . . . . . . . . .13 1.2.1 Serial Host Interface SPI Protocol Timing . . . . . . . 14 1.2.2 Serial Host Interface (SHI) I2C Protocol Timing . . 20 1.2.3 Programming the SHI I2C Serial Clock . . . . . . . . . 22 1.2.4 Enhanced Serial Audio Interface Timing . . . . . . . . 23 1.2.5 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.2.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 3 4 1.2.7 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . . . 1.2.8 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.9 EMC Timing Specifications--DSP56724 . . . . . . . . Functional Description and Application Information . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Pinout and Package Information . . . . . . . . . . . . . . . . . 4.1.1 Pinout for DSP56724 144-Pin Plastic LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Pinout for DSP56725 80-Pin Plastic LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 144-Pin Package Outline Drawing . . . . . . . . . . . . . . . . 4.3 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 38 38 38 39 39 40 40 41 43 45 45
5 6
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 2 Freescale Semiconductor
EXTAL/XTAL
Chip Config
ESAI_1
ESAI_2
ESAI_3
S/PDIF
WDT_1
TEC_1
GPIO
SHI_1
ESAI
WDT
DSP Core-0
On-Chip Memory
GPIO
EMC
CGM
ASRC
DSP Core-1
On-Chip Memory
Arbiter 9
Arbiter 8
P
X
Y
Shared Bus 0 Shared Bus 1
Arbiters 0-7
P
X
Y
PCU / AGU / ALU
DMA
OnCE
Shared Memory 4 Kbytes Blocks 0-7 (32 Kbytes total)
OnCE
PCU / AGU / ALU
DMA
MODA0, MODB0, MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1, MODC1, MODD1
Figure 1. DSP56724 Block Diagram
EXTAL/XTAL
Chip Config
ESAI_1
ESAI_2
ESAI_3
S/PDIF
WDT_1
TEC_1
GPIO
SHI_1
ESAI
WDT
DSP Core-0
On-Chip Memory
GPIO
CGM
ASRC
DSP Core-1
On-Chip Memory
Arbiter 8
Shared Bus 0 P X Y
Arbiters 0-7
Shared Bus 1 P X Y
PCU / AGU / ALU
DMA
OnCE
Shared Memory 4 Kbytes Blocks 0-7 (32 Kbytes total)
OnCE
PCU / AGU / ALU
DMA
MODA0, MODB0, MODC0, MODD0
2 JTAGs
JTAG
MODA1, MODB1, MODC1, MODD1
Figure 2. DSP56725 Block Diagram
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 3
GPIO
TEC
SHI
GPIO
TEC
SHI
1
1.1
Electrical Characteristics
Chip-Level Conditions
Table 1. Chip-Level Conditions
For Section 1.1.1, "Maximum Ratings" Section 1.1.2, "Thermal Characteristics" Section 1.1.3, "Power Requirements" Section 1.1.4, "DC Electrical Characteristics" Section 1.1.5, "AC Electrical Characteristics" Section 1.1.6, "Internal Clocks" Section 1.1.7, "External Clock Operation" Section 1.1.8, "Reset, Stop, Mode Select, and Interrupt Timing" See on page 4 on page 6 on page 6 on page 7 on page 8 on page 8 on page 9 on page 10
Table 1 provides a quick reference to the subsections in this section.
1.1.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (for example, either GND or VDD). The suggested value for a pull-up or pull-down resistor is 4.7 k.
NOTE
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 4 Freescale Semiconductor
Table 2 lists the maximum ratings. Table 2. Maximum Ratings
Rating1 Supply Voltage Symbol VCORE_VDD, VPLLD_VDD VPLLP_VDD, VIO_VDD, VIO_VDD_25, VPLLA_VDD Maximum CORE_VDD power supply ramp time Input Voltage per pin excluding VDD and GND Current drain per pin excluding VDD and GND (Except for pads listed below) LSYNC_OUT LCLK LALE TDO Operating temperature range * Fsys < 200 MHz * Fsys < 250 MHz Storage temperature ESD protected voltage (Human Body Model) ESD protected voltage (Charged Device Model) * All pins * Corner pins Tr VIN I Ilsync_out Ilclk Iale IJTAG TJ -40 to +100 0 to 90 TSTG -- -- 500 750 -65 to +150 2000 Value1, 2 -0.3 to + 1.26 -0.3 to + 4.0 10 GND - 0.3 to 5.5 V 12 5 5 5 12 Unit V V ms V mA mA mA mA mA
C C
V V
Note: 1. GND = 0 V, TJ = -40 C to 100 C, CL = 50 pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 5
1.1.2
Thermal Characteristics
Table 3. Thermal Characteristics
Characteristic Symbol RJA or JA LQFP Values 57 for 80 QFP 49 for 144 QFP 44 for 80 QFP 40 for 144 QFP RJC or JC 10 for 80 QFP 9 for 144 QFP Unit
Table 3 lists the thermal characteristics.
Natural Convection, Junction-to-ambient thermal Single layer board resistance1,2 (1s) Four layer board (2s2p) Junction-to-case thermal resistance3 --
C/W C/W C/W
Note: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
1.1.3
Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode as shown in Figure 3, connected between the DSP56724/DSP56725 IO_VDD and Core_VDD power pins.
IO_VDD External Schottky Diode Core_VDD
Figure 3. Prevent High Current Conditions by Using External Schottky Diode If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead of Core_VDD, as shown in Figure 4.
Core_VDD
IO_VDD
Figure 4. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 6 Freescale Semiconductor
For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms, as shown in Figure 4.
Tr 1.0 V
Core_VDD
0V Tr must be < 10 ms
Figure 5. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
1.1.4
DC Electrical Characteristics
Table 4. DC Electrical Characteristics
Characteristics Symbol VCORE_VDD, VPLLD_VDD VIO_VDD, VPLLP_VDD, VPLLA_VDD VIH Min 0.95 1.14 3.14 Typ 1.0 1.2 3.3 Max 1.05 1.26 3.45 V Unit V
Core Supply voltages * Fsys < 200 MHz * Fsys < 250 MHz IO Supply voltages
Input high voltage
2.0
--
VIO_VDD + 2V
V
Note: To avoid a high current condition and possible system damage, all 3.3-V and 2.5-V supplies must rise before the 1.0-V supplies rise. Input low voltage Input leakage current Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.3 V or 0 V) Output high voltage IOH = -12 mA LSYNC_OUT, LALE, LCLK Pins IOH = -16 mA, TDO Pin IOH = -24 mA Output low voltage IOL = 12 mA LSYNC_OUT, LALE, LCLK Pins IOL = 16 mA, TDO Pins IOL = 24 mA Internal pull-up resistor Internal pull-down resistor Internal supply Fsys < 200 MHz * In Normal mode * In Wait mode current1 (core only) operating at mA ICCI ICCW -- -- 90 60 280 250 mA RPU RPD 63 57 92 91 142 159 k k VOL -- -- 0.4 V VIL IIN CIN ITSI VOH -0.3 -- -- -10 2.4 -- -- 2.057 -- -- 0.8 80 -- 10 -- V A pF A V
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 7
Table 4. DC Electrical Characteristics (Continued)
Characteristics * In Stop mode2 Internal supply Fsys < 250 MHz * In Normal mode * In Wait mode * In Stop mode
2
Symbol ICCS
Min --
Typ 30
Max 220
Unit mA
current1
(core only) operating at ICCI ICCW ICCS CIN -- -- -- -- 140 90 40 -- 340 290 240 10 mA mA mA pF
Input capacitance
Note: 1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (for example, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current with Fsys < 200 MHz is measured with VCORE_VDD = 1.0 V, VDD_IO = 3.3 V at TJ = 25 C. Maximum internal supply current is measured with VCORE_VDD = 1.05 V, VIO_VDD) = 3.6 V at TJ = 100 C. Typical internal supply current with Fsys < 250 MHz is measured with VCORE_VDD = 1.2 V, VDD_IO = 3.3 V at TJ = 25 C. Maximum internal supply current is measured with VCORE_VDD = 1.26 V, VIO_VDD) = 3.6 V at TJ = 90 C. 2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (that is, not allowed to float).
1.1.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V IL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. For all pins, output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.
1.1.6
Internal Clocks
Table 5. Internal Clocks
Table 5 lists the internal clocks.
No. 1 2
Characteristics Comparison Frequency Input Clock Frequency * with PLL enabled * with PLL disabled
Symbol Fref Fin
Min 2 2 --
Typ -- --
Max 8 248 200
Unit MHz MHz
Condition Fref = Fin/NR --
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 8 Freescale Semiconductor
Table 5. Internal Clocks (Continued)
No. 3 4 Characteristics PLL VCO Frequency Output Clock Frequency * with PLL enabled * with PLL disabled
[1] [2]
Symbol Fvco Fout
Min 200 25 --
Typ -- --
Max 500 200 or 250 200 or 250
Unit MHz MHz
Condition Fvco = (Fin * NF)/NR Fout = Fvco/NO Fout = Fin Fsys = Fout/2DF Fsys = Fout
5
System Clock Frequency * with PLL enabled[2] * with PLL disabled
Fsys 0.195 0
-- 200 or 250 200 MHz
Note: 1. Fin = External frequency NF = Multiplication Factor NR = Predivision Factor NO = Output Divider DF = Division Factor 2. Maximum frequency of 200 MHz supported at 0.95 V < VVDD_CORE < 1.05 V and -40 < Tj < 100 C Maximum frequency of 250 MHz supported at 1.14 V < VVDD_CORE < 1.26 V and 0 < Tj < 90 C
1.1.7
External Clock Operation
The DSP56724/DSP56725 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see Figure 6.
EXTAL XTAL Suggested component values: = 24.576 MHz R = 1 M 10% C (EXTAL)= 18 pF C (XTAL) = 18 pF C Calculations are for a 5-30 MHz crystal with the following parameters: * shunt capacitance (C0) of 10 pq-F12 pF * series resistance 40 Ohm * drive level of 10 W
fosc
R
C
XTAL1
Figure 6. Using the On-Chip Oscillator If the DSP56724/DSP56725 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 7). When the external square wave source is connected to EXTAL, the XTAL pin is not used.
VIH
EXTAL VIL Eth
Etl 6 8 Note: The midpoint is 0.5 (VIH + VIL). 7 Etc
Midpoint
Figure 7. External Clock Timing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 9
Table 6 lists the clock operation. Table 6. Clock Operation
No. 6 Characteristics EXTAL input high 1 (40% to 60% duty cycle) * Crystal oscillator * Square wave input EXTAL input low 1 (40% to 60% duty cycle) * Crystal oscillator * Square wave input EXTAL cycle time * With PLL disabled * With PLL enabled Instruction cycle time * With PLL disabled * With PLL enabled Symbol Min Max Units
Eth
16.67 2.5
100 inf
ns
7
Etl
16.67 2.5 5 33.3 5 44
100 inf inf 500 inf 5120
ns
8
Etc
ns
9
Tc
ns
Note: 1. Measured at 50% of the input transition. 2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 3. Maximum frequency of 200 MHz supported at 0.95 V < VVDD_CORE < 1.05 V and -40 < Tj < 100 C Maximum frequency of 250 MHz supported at 1.14 V < VVDD_CORE < 1.26 V and 0 < Tj < 90 C 4. PLLLOCK = 200 s.
1.1.8
Reset, Stop, Mode Select, and Interrupt Timing
Table 7. Reset, Stop, Mode Select, and Interrupt Timing
Table 7 lists the reset, stop, mode select, and interrupt timing.
No. 10 11
Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled Syn reset deassert delay time * Minimum * Maximum (PLL enabled)
Expression -- 2 x TC 2 x TC 2 x TC (2xTC)+PLLLOCK -- -- -- -- 10 x TC + 4
Min -- 10 10 10 200 10 12 7 4 54
Max 11 -- -- -- -- -- -- -- -- --
Unit ns ns ns ns us ns ns ns ns ns
13
14 15 16 17 18
Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from interrupt trigger to interrupt code execution
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Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
No. 19 Characteristics Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 1 Interrupt Requests Rate1 * ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1 * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 22 DMA Requests Rate * Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 * Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 * Timer, Timer_1 * IRQ, NMI (edge trigger) Expression Min Max Unit
(128 Kbytes x TC) 25 x TC (128KxTC) + PLLLOCK (25 x TC) + PLLLOCK 10 x TC + 3.8
655 125 855 200 --
-- -- -- -- 53.8
s ns s s ns
21
12 x TC 8 x TC 8 x TC 12 x TC 6 x TC 7 x TC 2 x TC 3 x TC
-- -- -- -- -- -- -- --
60.0 40.0 40.0 60.0 30.0 35.0 10.0 15.0
ns ns ns ns ns ns ns ns
Note: 1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us. 3. Periodically sampled and not 100% tested. 4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 11
Figure 8 shows the reset timing diagram.
VIH RESET
11 10 All Pins Reset Value
13
Figure 8. Reset Timing Figure 9 shows external fast interrupt timing diagram.
a) First Interrupt Instruction Execution
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
19
18
b) General Purpose I/O
General Purpose I/O
20 IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
Figure 9. External Fast Interrupt Timing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 12 Freescale Semiconductor
Figure 10 shows external interrupt timing (negative edge-triggered).
IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 16 IRQA, IRQB, IRQC, IRQD, NMI, NMI_1
17
Figure 10. External Interrupt Timing (Negative Edge-Triggered) Figure 11 shows MODE select set-up and hold time diagram.
RESET VIH
14 15 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQC,IRQD, NMI
Figure 11. MODE Select Set-Up and Hold Time
1.2
Module-Level Specifications
Table 8. Module-Level Specifications
For Section 1.2.1, "Serial Host Interface SPI Protocol Timing" Section 1.2.2, "Serial Host Interface (SHI) I2C Protocol Timing" Section 1.2.3, "Programming the SHI I2C Serial Clock" See on page 4 on page 6 on page 6 on page 7 on page 28 on page 29 on page 31 on page 32 on page 33
Table 8 provides a quick reference to the subsections of this section.
Section 1.2.4, "Enhanced Serial Audio Interface Timing" Section 1.2.5, "GPIO Timing" Section 1.2.6, "JTAG Timing" Section 1.2.7, "Watchdog Timer Timing" Section 1.2.8, "S/PDIF Timing" Section 1.2.9, "EMC Timing Specifications--DSP56724"
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 13
1.2.1
Serial Host Interface SPI Protocol Timing
Table 9. Serial Host Interface SPI Protocol Timing
Table 9 lists the serial host interface SPI protocol timing.
No. 23
Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min)
Mode Master/Slave
Filter Mode Bypassed Very Narrow Narrow Wide
Expression 10 x TC + 9 10 x TC + 9 10 x TC + 133 10 x TC + 333 -- -- -- -- 0.5 x (tSPICC) 0.5 x (tSPICC) 0.5 x (tSPICC) 0.5 x (tSPICC) 2.5 x TC + 12 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 0.5 x (tSPICC) 0.5 x (tSPICC) 0.5 x (tSPICC) 0.5 x tSPICC) 2.5 x TC + 12 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 -- --
Min 59.0 59.0 183.0 383.0 -- -- -- -- 29.5 29.5 91.5 191 24 24 114.5 201.5 29.5 29.5 91.5 191 24 24 114.5 201.5 -- --
Max -- -- -- -- 0 10 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
XX Tolerable Spike width on data or clock in.
--
Bypassed Very Narrow Narrow Wide
24
Serial clock high period
Master
Bypassed Very Narrow Narrow Wide
Slave
Bypassed Very Narrow Narrow Wide
25
Serial clock low period
Master
Bypassed Very Narrow Narrow Wide
Slave
Bypassed Very Narrow Narrow Wide
26
Serial clock rise/fall time
Master Slave
-- --
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 14 Freescale Semiconductor
Table 9. Serial Host Interface SPI Protocol Timing (Continued)
No. 27 Characteristics1,3,4 SS assertion to first SCK edge CPHA = 0 Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide CPHA = 1 Slave Bypassed Very Narrow Narrow Wide 28 Last SCK edge to SS not asserted Slave Bypassed Very Narrow Narrow Wide 29 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed Very Narrow Narrow Wide 30 SCK last sampling edge to data input not valid Master /Slave Bypassed Very Narrow Narrow Wide 31 32 33 SS assertion to data out active SS deassertion to data high SCK edge to data out valid (data out delay time) impedance2 Slave Slave Master /Slave -- -- Bypassed Very Narrow Narrow Wide 34 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed Very Narrow Narrow Wide 35 SS assertion to data out valid (CPHA = 0) Slave -- Expression 3.5 x TC + 15 3.5 x TC + 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 x TC + 10 2 x TC + 30 2 x TC + 60 -- -- -- -- -- -- -- -- -- -- -- -- Min 32.5 22.5 0 0 10 0 0 0 12 22 100 200 0 0 0 0 20 40 70 100.0 5 -- -- -- -- -- 11.67 15 55 105 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 46.2 270 376 521 -- -- -- -- 14.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 15
Table 9. Serial Host Interface SPI Protocol Timing (Continued)
No. 36 Characteristics1,3,4 First SCK sampling edge to HREQ output deassertion Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Very Narrow Narrow Wide 38 39 40 41 42 43 SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) HREQ assertion width Slave Slave Master Master Master Master -- -- -- -- -- -- Expression -- -- -- -- -- -- -- -- -- TC + 6 0.5 x TSPICC + 3.0 x TC + 43 -- -- 3.0 x TC Min 45 55 95 145 50.0 60.0 100.0 150.0 45.0 11.0 96.0 0 0 15 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. 0.95 V < VVDD_CORE < 1.05 V and T J < 100 C, CL = 50 pF 2. Periodically sampled, not 100% tested 3. All times assume noise free inputs. 4. All times assume internal clock frequency of 200 MHz. 5. SHI_1 specs match those of SHI 6. Slave timings should equal the serial clock high period + the serial clock low period.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 16 Freescale Semiconductor
Figure 12 shows the SPI master timing (CPHA = 0).
SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB m29 LSB Valid 34 LSB 30 23 26 26 26 23 26
Figure 12. SPI Master Timing (CPHA = 0)
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 17
Figure 13 shows the SPI master timing (CPHA = 1).
SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB 41 LSB Valid 34 LSB 29 30 26 23 26 26 23 26
Figure 13. SPI Master Timing (CPHA = 1)
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 18 Freescale Semiconductor
Figure 14 shows the SPI slave timing (CPHA = 0).
SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 35 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 38 34 MSB 29 30 33 34 LSB 32 23 26 26 26 23 26 39 28
Figure 14. SPI Slave Timing (CPHA = 0)
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 19
Figure 15 shows the SPI slave timing (CPHA = 1).
SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 33 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 37 MSB 29 30 33 34 32 LSB 26 26 26 23 26 28
Figure 15. SPI Slave Timing (CPHA = 1)
1.2.2
Serial Host Interface (SHI) I2C Protocol Timing
Table 10. SHI I2C Protocol Timing
Standard I2C Characteristics1,2,3,4,5 Symbol/ Expression -- -- -- -- -- FSCL TSCL TBUF TSUSTA -- 10 4.7 4.7 0 10 50 100 100 -- -- -- -- -- -- -- -- 2.5 1.3 0.6 0 10 50 100 400 -- -- -- ns ns ns ns kHz s s s Standard Min Max Fast-Mode Unit Min Max
Table 10 lists the SHI I 2C protocol timing diagram.
No.
XX Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Filters enabled. 44 44 45 46 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 20 Freescale Semiconductor
Table 10. SHI I2C Protocol Timing (Continued)
Standard I2C Characteristics1,2,3,4,5 Start condition hold time SCL low period SCL high period SCL and SDA rise time 7 Symbol/ Expression THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT FOSC 10.6 10.6 11.8 13.1 TVD;DAT TSU;STO tSU;RQI TNG;RQO 4 x TC + 30 4 x TC + 50 4 x TC + 130 4 x TC + 230 TAS;RQO 2 x TC + 30 2 x TC + 40 2 x TC + 80 2 x TC + 130 40 50 90 140 -- -- -- -- 40 50 90 140 -- -- -- -- ns ns ns ns -- -- -- -- 50.0 70.0 250.0 150.0 -- -- -- -- 50.0 70.0 150.0 250.0 ns ns ns ns -- 4.0 0.0 -- -- -- -- 3.4 -- -- 28.5 28.5 39.7 61.0 -- 0.6 0.0 -- -- -- -- 0.9 -- -- MHz MHz MHz MHz s s ns Standard Min 4.0 4.7 4.0 -- -- 250 0.0 Max -- -- -- 1000 5.0 -- -- Fast-Mode Unit Min 0.6 1.3 1.3 -- -- 100 0.0 Max -- -- -- 300 5.0 -- 0.9 s s s ns ns ns s
No. 47 48 49 50 51 52 53 54
SCL and SDA fall time7 Data set-up time Data hold time DSP clock frequency * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled
55 56 57 58
59
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 21
Table 10. SHI I2C Protocol Timing (Continued)
Standard I2C Characteristics1,2,3,4,5 HREQ in assertion to first SCL edge * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled First SCL edge to HREQ is not asserted (HREQ in hold time.) Symbol/ Expression TAS;RQI 4327 4317 4282 4227 tHO;RQI 0.0 -- -- -- -- -- 927 917 877 827 0.0 -- -- -- -- -- ns ns ns ns ns Standard Min Max Fast-Mode Unit Min Max
No. 60
61
Note: 1. VCORE_VDD = 1.00 0.05 V; TJ = -40 C to 100 C, C L = 50 pF 2. Pull-up resistor: R P (min) = 1.5 k 3. Capacitive load: C b (max) = 50 pF 5. All times assume noise free inputs 5. All times assume internal clock frequency of 200 MHz 6. SHI_1 specs match those of SHI 7. The numbers listed are based on the module/pad design and its characteristics during output. The module is compliant with I2C standard, so the module should receive I2C bus compliant signal without any issue.
1.2.3
Programming the SHI I2C Serial Clock
The programmed serial clock cycle, T I2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] where -- HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC (if HDM[7:0] = $02 and HRS = 1) to 4096 x TC (if HDM[7:0] = $FF and HRS = 0)
Eqn. 1
Eqn. 2
Eqn. 3
The programmed serial clock cycle (TI2CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in next. TI2CCP + 3 x TC + 45ns + TR
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
Eqn. 4
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 22 Freescale Semiconductor
Figure 16 shows the I2C timing diagram.
44 46 SCL 50 45 52 SDA Stop Start 47 61 60 HREQ MSB 58 57 59 LSB 55 ACK 56 Stop 51 53 49 48
Figure 16. I2C Timing
1.2.4
Enhanced Serial Audio Interface Timing
Table 11. Enhanced Serial Audio Interface Timing
Table 11 lists the enhanced serial audio interface timing.
No. 62 63 Clock cycle5
Characteristics1, 2, 3
Symbol Expression3 tSSICC 4 x Tc 4 x Tc 2 x Tc 2 x Tc 2 x Tc 2 x Tc -- -- -- -- -- --
Min 20.0 20.0 10 10 10 10 -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 17.0 7.0
Condition4 Unit i ck i ck -- -- ns -- -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a ns ns ns ns ns ns ns ns
Clock high period * For internal clock * For external clock
-- -- -- -- -- -- -- -- -- --
64
Clock low period * For internal clock * For external clock
65 66 67 68 69 70
SCKR rising edge to FSR out (bl) high SCKR rising edge to FSR out (bl) low SCKR rising edge to FSR out (wr) high6 SCKR rising edge to FSR out (wr) low6 SCKR rising edge to FSR out (wl) high SCKR rising edge to FSR out (wl) low
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 23
Table 11. Enhanced Serial Audio Interface Timing (Continued)
No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Characteristics1, 2, 3 Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge FSR input (bl, wr) high before SCKR falling edge 6 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge Flags input setup before SCKR falling edge Flags input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high SCKT rising edge to FST out (bl) low SCKT rising edge to FST out (wr) high6 SCKT rising edge to FST out (wr) low6 SCKT rising edge to FST out (wl) high SCKT rising edge to FST out (wl) low SCKT rising edge to data out enable from high impedance SCKT rising edge to transmitter #0 drive enable assertion SCKT rising edge to data out valid SCKT rising edge to data out high impedance7 SCKT rising edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before SCKT falling edge6 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge Symbol Expression3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min 12.0 19.0 3.5 9.0 2.0 12.0 2.0 12.0 2.5 8.5 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 18.0 2.0 18.0 4.0 5.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18.0 8.0 20.0 10.0 20.0 10.0 22.0 12.0 15.0 9.0 15.0 10.0 22.0 17.0 17.0 11.0 25.0 13.0 25.0 16.0 14.0 9.0 -- -- -- -- -- -- Condition4 Unit x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 24 Freescale Semiconductor
Table 11. Enhanced Serial Audio Interface Timing (Continued)
No. 92 93 94 95 96 97 Characteristics1, 2, 3 FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion Flag output valid after SCKT rising edge HCKR/HCKT clock cycle HCKT input rising edge to SCKT output HCKR input rising edge to SCKR output Symbol Expression3 -- -- -- -- -- -- -- -- -- 2 x TC -- -- Min -- -- -- -- 10 -- -- Max 21.0 14.0 14.0 9.0 -- 18.0 18.0 Condition4 Unit -- -- x ck i ck -- -- -- ns ns ns ns ns ns
Note: 1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100 C, CL = 50 pF 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested. 8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 25
Figure 17 shows the ESAI transmitter timing diagram.
62 63 SCKT (Input/Output) 78 FST (Bit) Out 82 FST (Word) Out 83 79 64
86 84
86 87 First Bit Last Bit
Data Out 93 Transmitter #0 Drive Enable (Internal Signal)
89 91
85
88
FST (Bit) In 92 90 FST (Word) In 94 See Note 91
Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 17. ESAI Transmitter Timing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 26 Freescale Semiconductor
Figure 18 shows the ESAI receiver timing diagram.
62 63 SCKR (Input/Output) 65 FSR (Bit) Out 69 FSR (Word) Out 72 71 Data In First Bit 73 FSR (Bit) In 74 FSR (Word) In 76 Flags In 77 75 75 Last Bit 70 64
66
Figure 18. ESAI Receiver Timing Figure 19 shows the ESAI HCKT timing diagram.
HCKT
SCKT(output)
95
96
Figure 19. ESAI HCKT Timing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 27
Figure 20 shows the ESAI HCKR timing diagram.
HCKR
SCKR (output)
95
97
Figure 20. ESAI HCKR Timing
1.2.5
GPIO Timing
Table 12. GPIO Timing
No. 100 101 102 103 104 105 106 107 Characteristics1 Fsys edge to GPIO out valid (GPIO out delay time)2 Fsys edge to GPIO out not valid (GPIO out hold time) Fsys In valid to EXTAL edge (GPIO in set-up Fsys edge to GPIO in not valid (GPIO in hold Minimum GPIO pulse high width Minimum GPIO pulse low width GPIO out rise time GPIO out fall time time)2 time)2
2
Table 12 lists the GPIO timing.
Expression -- -- -- -- 2 x TC 2 x TC -- --
Min -- -- 2 0 10 10 -- --
Max 7 7 -- -- -- -- 13.0 13.0
Unit ns ns ns ns ns ns ns ns
Note: 1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100 C, CL = 50 pF 2. Simulation numbers-subject to change.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 28 Freescale Semiconductor
Figure 21 shows the GPIO timing diagram.
Fsys 100 101 GPIO (Output) 102 GPIO (Input) GPIO (Output) 104 106 105 107 Valid 103
Figure 21. GPIO Timing
1.2.6
JTAG Timing
Table 13. JTAG Timing
All Frequencies No. 108 109 110 111 112 113 114 115 116 117 118 119 Characteristics Min TCK frequency of operation (1/(TC x 3); maximum 10 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.65 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance -- 100.0 50.0 -- 15.0 24.0 -- -- 5.0 25.0 -- -- Max 10.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 MHz ns ns ns ns ns ns ns ns ns ns ns Unit
Table 13 lists the JTAG timing.
Note: 1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100 C, CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 29
Figure 22 shows the text clock input timing diagram.
109 110 TCK (Input) VIH 111 VM VIL 111 110 VM
Figure 22. Test Clock Input Timing Diagram Figure 23 shows the debugger port timing diagram.
TCK (Input) VIH VIL 112 Data Inputs 114 Data Outputs 115 Data Outputs 114 Data Outputs Output Data Valid Output Data Valid Input Data Valid 113
Figure 23. Debugger Port Timing Diagram
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 30 Freescale Semiconductor
Figure 24 shows the test access port timing diagram.
TCK (Input) TDI TMS (Input) 118 TDO (Output) 119 TDO (Output) 118 TDO (Output) Output Data Valid Output Data Valid VIH VIL 116 Input Data Valid 117
Figure 24. Test Access Port Timing Diagram
1.2.7
Watchdog Timer Timing
Table 14. Watchdog Timer Timing
Table 14 lists the watchdog timer timings.
No. 120 121
Characteristics Delay from time-out to fall of WDT, WDT_1 Delay from timer clear to rise of WDT, WDT_1
Expression 2 x Tc 2 x Tc
Min 10.0 10.0
Max -- --
Unit ns ns
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 31
1.2.8
S/PDIF Timing
Table 15. S/PDIF Timing
All Frequency Characteristics Symbol Min Max 0.7 ns -- -- Unit
Table 15 lists the S/PDIF timing.
SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew: asynchronous inputs, no specs apply SPDIFOUT1,SPDIFOUT2 output (Load = 50pf) * Skew * Transition Rising * Transition Falling SPDIFOUT1, SPDIFOUT2 output (Load = 30pf) * Skew * Transition Rising * Transition Falling SRCK period SRCK high period SRCK low period STCLK period STCLK high period STCLK low period
-- -- -- -- -- -- srckp srckph srckpl stclkp stclkph stclkpl
-- -- --
1.5 24.2 31.3
ns
-- -- -- 40.0 16.0 16.0 40.0 16.0 16.0
1.5 13.6 18.0 -- -- -- -- -- --
ns
ns ns ns ns ns ns
Figure 25 shows the SRCK timing diagram.
srckp srckpl SRCK (Output) VM srckph VM
Figure 25. SRCK Timing Figure 26 shows the STCLK timing diagram.
stclkp stclkpl STCLK (Input) VM stclkph VM
Figure 26. STCLK Timing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 32 Freescale Semiconductor
1.2.9
EMC Timing Specifications--DSP56724
NOTE
The DSP56725 device does not have an EMC module. Table 16. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Parameter Symbol Tclk Tclk_skew Tin_s Tin_h Tgta Tupwait Tale_h Tale Tout_s Tout_h Tad_s Tad_h Tad_z Min 2 x Tc -- 3 2 12 12 3 3.8 4 2 3.5 1.5 -- Max -- 160 -- -- -- -- -- -- -- -- -- -- 4.3 Unit ns ps ns ns ns ns ns ns ns ns ns ns ns
Table 16 lists the EMC timing parameters with EMC PLL enabled.
LCLK cycle time LCLK skew to LSYNC_OUT Input setup to LSYNC_IN (except LGTA/LUPWAIT) Input hold from LSYNC_IN (except LGTA/LUPWAIT) LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time Output setup from LSYNC_IN (except LAD[23:0] and LALE) Output hold from LSYNC_IN (except LAD[23:0] and LALE) LAD[23:0] output setup from LSYNC_IN LAD[23:0] output hold from LSYNC_IN LSYNC_IN to output high impedance for LAD[23:0]
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 33
Figure 27 shows the EMC signals diagram, with EMC PLL enabled.
Tclk LCLK Tclk_skew LSYNC_OUT
Tsync_in_skew LSYNC_IN
Tin_s Tin_h
LAD[23:0] (data)
asynchronous input
LGTA
Tgta
asynchronous input
LUPWAIT
Tupwait
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 27. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 34 Freescale Semiconductor
Table 17 lists the EMC timing parameters with EMC PLL bypassed. Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Parameter LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA/LUPWAIT)1 LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time Output setup from LCLK (except LAD[23:0] and LALE) Output hold from LCLK (except LAD[23:0] and LALE) LAD[23:0] output setup from LCLK LAD[23:0] output hold from LCLK LCLK to output high impedance for LAD[23:0] Symbol Tclk Tin_s Tin_h Tgta Tupwait Tale_h Tale Tout_s Tout_h Tad_s Tad_h Tad_z Min 4 x Tc 8 -1 22 22 4 14 9 8 8 7 -- Max -- -- -- -- -- -- -- -- -- -- -- 8.1 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note: Negative hold time means the signal could be invalid before LCLK rising edge.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 35
Figure 28 shows the EMC signals diagram, with EMC PLL bypassed.
Tclk LCLK
Tin_s Tin_h
LAD[23:0] (data)
asynchronous input
LGTA
Tgta
asynchronous input
LUPWAIT
Tupwait
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 28. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4 Table 18 lists the EMC timing parameters with EMC PLL bypassed. Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Parameter LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time LGTA/LUPWAIT)1 Symbol Tclk Tin_s Tin_h Tgta Tupwait Tale_h Tale Min 8 x Tc 8 -1 42 42 5 34 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 36 Freescale Semiconductor
Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Parameter Output setup from LCLK (except LAD[23:0] and LALE) Output hold from LCLK (except LAD[23:0] and LALE) LAD[23:0] output setup from LCLK LAD[23:0] output hold from LCLK LCLK to output high impedance for LAD[23:0] Symbol Tout_s Tout_h Tad_s Tad_h Tad_z Min 19 18 18 17 -- Max -- -- -- -- 17.1 Unit ns ns ns ns ns
Note: 1. Negative hold time means the signal could be invalid before LCLK raising edge.
Figure 29 shows the EMC signals diagram, with EMC PLL bypassed.
Tclk LCLK
Tin_s Tin_h
LAD[23:0] (data)
asynchronous input
LGTA
Tgta
asynchronous input
LUPWAIT
Tupwait
Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0]
Tout_s
Tout_h
Tad_z Tad_s Tad_h
LAD[23:0]
Tale
LALE
Tale_h
Figure 29. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 37
2
Functional Description and Application Information
Refer to the SymphonyTM DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM) for detailed functional and applications information.
3
Ordering Information
Table 19. Ordering Information
Device DSP56724 DSP56724 DSP56725 DSP56725 Device Marking DSPB56724AG DSPB56724CAG DSPB56725AF DSPB56725CAF Ambient Temp. 0 C-70 C -40 C-85 C 0 C-70 C -40 C-85 C Speed 250 MHz 200 MHz 250 MHz 200 MHz Voltage 1.14-1.26 V 0.95-1.05 V 1.14-1.26 V 0.95-1.05 V LQFP Package 20 mm x 20 mm 20 mm x 20 mm 14 mm x 14 mm 14 mm x 14 mm
Table 19 shows the ordering information for the DSP56724/DSP56725 devices.
Contact your local Freescale sales representative for ordering information.
4
Package Information
Table 20. Package Outline Drawings
Device DSP56724 DSP56725 Package See
This section provides package and pinout information. Table 20 is a quick reference to the package outline drawings.
144-pin plastic LQFP See Section 4.2, "144-Pin Package Outline Drawing," on page 41. 80-pin plastic LQFP See Section 4.3, "80-Pin Package Outline Drawing," on page 43.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 38 Freescale Semiconductor
4.1
Pinout and Package Information
This section provides information about the available package for DSP56724 and DSP56725 devices, including diagrams of the package pinouts. See Figure 30 for the DSP56724 pin assignments and Figure 31 for the DSP56725 pin assignments. For more detailed information about signals, refer to the SymphonyTM DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM).
4.1.1
Pinout for DSP56724 144-Pin Plastic LQFP Package
SCAN MODA0/IRQA MODB0/IRQB MODC0/PLOCK MODD0/PG1 FSR_3 SCKR_3 HCKR_3 SCKT_3 FST_3 HCKT_3 IO_GND IO_VDD CORE_GND CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 MODD1/PG2 SDO2_2/SDI3_2 SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 RESET CORE_GND CORE_VDD CORE_VDD CORE_GND LALE LCS0 LCS1 LCS2 LCS3 LCS4 LCS5 LCS6 LCS7 IO_VDD IO_GND CORE_VDD CORE_GND LWE LOE LGPL5 LSDA10 LCKE LCLK LBCTL LSDWE LSDCAS LGTA LA0 LA1 LA2 IO_VDD IO_GND PLLP1_GND PLLP1_VDD PLLD1_GND PLLD1_VDD PLLA1_GND PLLA1_VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
DSP56724 144-Pin
IO_GND IO_VDD WDT PINIT/NMI TDO TDI TCK TMS SDO2_1/SDI3_1 SDO3_1/SDI2_1 SDO4_1/SDI1_1 SDO5_1/SDI0_1 CORE_GND CORE_VDD FSR SCKR HCKR SCKT FST HCKT SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 SPDIFOUT1 SPDIFIN1 IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 39
LSYNC_IN LSYNC_OUT LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 CORE_VDD CORE_GND IO_VDD IO_GND LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 IO_VDD IO_GND CORE_VDD CORE_GND LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 IO_GND IO_VDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 30. DSP56724 144-Pin Package Pinout
4.1.2
Pinout for DSP56725 80-Pin Plastic LQFP Package
MODC0/PLOCK MODC1/NMI_1 MODA1/IRQC MODB1/IRQD MODA0/IRQA MODB0/IRQB CORE_GND SS_1/HA2_1 CORE_GND 62 CORE_VDD CORE_VDD 61 60 59 58 57 56 55 54 HREQ/PH4
IO_GND
IO_VDD
SS/HA2
MISO/SDA
MOSI/HA0
SCK/SCL
67
66
65
80
79
78
77
76
75
74
73
72
71
70
69
68
64
SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 IO_VDD IO_GND CORE_VDD CORE_GND SPDIFIN1/SDO2_2/SDI3_2 SPDIFOUT1/SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 FSR_3 SCKR_3 SCKT_3 GND GND GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 37 38 39 25 26 35 33 34 36 40
63
RESET
SCAN
WDT PINIT/NMI TDO TDI TCK TMS CORE_GND CORE_VDD SDO4/SDI1 SDO5/SDI0 IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD
DSP56725 80-Pin
53 52 51 50 49 48 47 46 45 44 43 42 41
SDO2_1/SDI3_1
SDO3_1/SDI2_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
CORE_GND
CORE_GND
CORE_VDD
CORE_VDD
SDO2/SDI3
Figure 31. DSP56725 80-Pin Package
4.1.3
Pin Multiplexing
Many pins are multiplexed, and depending on the selected configuration, can be one of three possible signals. For more about pin multiplexing, refer to the SymphonyTM DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM).
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 40 Freescale Semiconductor
SDO3/SDI2
FSR
HCKR
SCKR
IO_VDD
IO_GND
SCKT
FST
FST_3
HCKT_3
HCKT
4.2
144-Pin Package Outline Drawing
The 144-pin package outline drawing is shown in Figure 32 and Figure 33.
Figure 32. 144-Pin Package Outline Drawing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 41
Figure 33. 144-Pin Package Outline Drawing (continued)
FIGURE NOTES: 1 All dimensions are in millimeters. 2 Interpret dimensions and tolerances per ASME Y.14.5M-1994 3 Datums B, C and D to be determined at datum plane H. 4 The top package body size may be smaller than the bottom package size by a maximum of 0.1 mm. 5 These dimensions do not include mold protrusions. The maximum allowable protrusion is 0.25 mm per side. These dimensions are maximum body size dimensions including mold mismatch. 6 This dimension does not include dam bar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm. Minimum space between protrusion and an adjacent lead shall be 0.07 mm. 7 These dimensions are determined at the seating plane, datum A.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 42 Freescale Semiconductor
4.3
80-Pin Package Outline Drawing
The 80-pin package outline drawing is shown in Figure 34 and Figure 35.
Figure 34. 80-Pin Package Outline Drawing
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 43
Figure 35. 80-Pin Package Outline Drawing (continued)
FIGURE NOTES: 1 Dimensioning and tolerancing per ASME Y.14.5M-1994. 2 Controlling dimension: millimeter. 3 Data plane H is located at the bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4 Datum E, F and to be determined at datum plane H. 5 Dimensions to be determined at seating plane C. 6 Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and are determined at datum plane H. 7 Dimension does not include dambar protrusion Dambar protrusion shall not cause the lead width to exceed 0.46 mm. Minimum space between protrusion and adjacent lead or protrusion is 0.07mm.
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 44 Freescale Semiconductor
5
Product Documentation
Table 21 lists the documents that provide a complete description of the DSP56724/DSP56725 devices and are required to design properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 21. DSP56724 / DSP56725 Documentation
Document Name DSP56300 Family Manual Description Order Number
Detailed description of the 56300-family architecture and the 24-bit DSP56300FM core processor and instruction set DSP56724RM DSP56724PB DSP56725PB DSP56724
DSP56724/DSP56725 Reference Manual Detailed description of memory, peripherals, and interfaces DSP56724 Product Brief DSP56725 Product Brief DSP56724/DSP56725 Data Sheet Brief description of the DSP56724 device Brief description of the DSP56725 device Electrical and timing specifications; pin and package descriptions (this document)
6
Revision History
Table 22. Revision History
Revision 1 Date 12/2008 Description * Modified values and removed rows in Table 4, "DC Electrical Characteristics." * Removed "IO_VDD_25" from Figure 4, "Prevent High Current Conditions by Applying IO_VDD Before Core_VDD." * In Table 7, "Reset, Stop, Mode Select, and Interrupt Timing," for No. 15, changed 10 to 12, and for No. 16, changed 4 to 7. * In Table 9, "Serial Host Interface SPI Protocol Timing," updated values. * In Table 10, "SHI I2C Protocol Timing," added note 7 and changed Max values for No. 50 to 1000 and 300; in addition, updated the values for note 1. * In Table 11, "Enhanced Serial Audio Interface Timing," for No. 82, changed 19 to 15; for No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25. * Removed Section 1.2.5, "Timer Timing." * In Table 16, "EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)," for "LSYNC_IN (except LGTA/LUPWAIT)," changed 2 to 3. * In Table 17, "EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)," for "LCLK to output high impedance for LAD [23:0]," changed 9 to 8.1. * In Table 18, "EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)," for LCLK to output high impedance for LAD [23:0]," changed 19 to 17.1 * In Table 19, "Ordering Information," added rows for DSPB56724CAG and DSPB56725CAF, and changed "DSPA56724AG" to "DSPB56724AG." * Initial public release.
Table 22 summarizes revisions to this document.
0
6/2008
SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 45
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SymphonyTM DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 47
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Rev. 1 12/2008

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